1. Field of the Invention
The present invention relates to information handling systems, and more particularly to information handling systems for processing graphics data for display on a display device.
2. Prior Art
There are many data processing systems in the prior art having graphics display capability. Some of the systems include graphics display subsystems such as the IBM 6095 graphics system which includes a frame buffer having two interleaved portions, wherein one portion is being loaded with new data while a second portion is being read to a display device.
An example of an attempt to improve performance of an interleaved dual frame buffer in a data processing system having a graphics display subsystem is described in an article entitled "Dual Frame Buffer Interleaving", Aranda and Henderson, IBM Technical Disclosure Bulletin, Vol. 36, No. 4, April 1993, pp. 53-58, inclusive.
In graphics display systems, pixels of a display are each represented by a value in a storage device referred to as a frame buffer. For a common high resolution display there are 1280 pixels in the horizontal direction by 1024 lines of pixels for a total of 1,310,720 pixels per display screen. Each pixels can be represented by from 1 to 24 bits for color or base plane data and 1 to 4 bits for overlay or attribute data. The frame buffer actually may have twice the number of bits to support the technique of interleaved buffering. Interleaved buffering is the technique of rendering to one set of locations in the buffer, for example, designated as frame buffer A while the other set of locations, designated as frame buffer B is being read to the display device.
The Aranda and Henderson article presents an architecture including a frame buffer organization which includes bandwidth for storing data to the video RAMs while supporting independent frame buffer selection on a per window basis.
A one megabit VRAM may be organized as 512 rows.times.512 columns.times.4 bits deep. Therefore, the number of VRAMs required to map a 1280.times.1024 screen is 5. Five VRAMs yield a single buffered 4 bit deep 1280.times.1024 frame buffer. To store 8 bit pixels, VRAMs are stacked 5 wide.times.2 deep. For a double buffer interleaved frame buffer, a second group of 5.times.2 VRAMs is added. If separate frame buffers are stored in separate VRAMs, the maximum number of pixels that can be stored in parallel is 5. If, however, 2 frame buffers are interleaved across both groups of VRAMs, the number of pixels that can be written simultaneously is increased to 10.
For non-windowed systems, either all of frame buffer A or frame buffer B is displayed to the display screen. The mapping of both frame buffers into VRAM is straight forward because data from both frame buffers is not required simultaneously at the output for transmission to the display device. For a typical graphics subsystem, frame buffers are mapped to VRAMs on an alternate column basis wherein each VRAM would contain half of its data assigned to frame buffer A and half of its data assigned to frame buffer B.
Although the article describes an improvement over other prior art video frame buffer architectures, the structure proposed in the article has several disadvantages. For example, the frame buffer requires five levels of logic and two separate clocks which are expensive in hardware and circuit complexity. Further, rendering of frame buffers A and B is staggered such that there is a delay between presentation of data from the two interleaved buffers.
Another prior art data processing system including efficient frame buffer architecture is described in U.S. patent application Ser. No. 08/330,294, filed Oct. 27, 1994 and now abandoned. The patent application describes a data processing system which has a frame buffer architecture for storing pixel data for display including a number of independently addressable storage units, the storage units being organized in a matrix having a number of rows and a number of columns wherein pixel data is spread across units in a row so that pixel data is distributed through a large number of independently addressable units in the frame buffer. The described system increases the effective bandwidth of the data bus carrying pixel data to the frame buffer by allowing a larger number of memory modules to be addressed concurrently.
Another frame buffer architecture includes mapping of pixels (or pels) to a VRAM to allow the buffer to be used for fast updating of blocks of 32.times.64 pixels. Eight VRAM chips each storing 1 megabit, with 4 bit input/output per chip is in common use in VRAMs. Many of the 1 megabit VRAM chips commercially available have four addressable islands on each chip. Thus, 8 bits of a pixel may be mapped on two such chips with one bit in each of the four islands on each chip.
For updating the screen, the buffer is accessed by applying the same address to all islands on a chip. Rows so accessed contain pixels of a 32.times.64 block on the screen. These bits are held in a page mode buffer and can be changed at the rate of 4 pixels (8 chips.times.4 bits per chip=32 bit) per page mode cycle. The page mode cycle is typically 3 to 5 times faster than the full access cycle so updating of the screen can proceed at a faster rate.
For accessing a line to refresh the screen, a diagonal section of bits must be accessed. This requires that each island on each chip be capable of accessing 32 separate rows each with a different stepped address. Thus, each island needs to be composed of 32 subislands for a total of 128 total subislands on the chip. With current VRAM chip layouts, there are far too few islands to make this mapping possible. A 1 megabit chip typically has 4 independent islands with no subislands. A 4 megabit chip typically has 16 independent islands, still far less than the required 128, and further only two such chips would be needed to produce a 1K.times.1K screen having 8 bits per pixel. If larger chips, with more islands having fewer bits per island, were to be available, such a mapping might be suitable. However, higher density chips typically use the previous generation chip image as an island and place multiples of such islands on the new chip to get the higher density. For example, a typical 1 megabit VRAM has 4 independent islands. The next generation of 4 megabit chips would map four of this 1 megabit macro as four islands to get the 4 times density. In order to get the kind of mapping required, it would be necessary to break the current island size into 32 smaller islands. While such a redesign is possible, it compromises the design optimization and is contrary to the evolutionary trend.
Therefore, this proposed mapping scheme is not practical with the current status and trend of chip designs.